The present invention relates to electronic circuits, and more particularly to controlling the phase bump a phased locked loop.
A phase locked loop maintains a fixed relationship between the phase and frequency of the signal it receives and those of the signal it generates. FIG. 1 is a simplified block diagram of a conventional phase locked loop (PLL) 10 adapted to maintain a fixed relationship between the phase and frequency of signal CLK and signal REF. PLL 10 includes, among other components, phase detector 12, charge pump 14, loop filter 16 and voltage controlled oscillator (VCO) 18. The extracted clock signal Clk is supplied at the output terminal of VCO 18. The operation of PLL 10 is described further below.
Phase detector 12 receives signals REF and Clk, and in response, generates signals UP and DN that correspond to the difference between the phases of the signals REF and Clk. Charge pump 14 receives signals UP and DN and in response varies the current it supplies to node Vcntrl. Loop filter 16 stores the charge as a voltage, which is then delivered to VCO 18.
If signal REF leads signal Clk in phase—indicating that the VCO is running relatively slowly—the duration of pulse signal UP increases, thereby causing charge pump 14 to increase its net output current I until VCO 18 achieves an oscillation frequency at which signal Clk is frequency-locked and phase-locked with signal REF. If, on the other hand, signal REF lags signal Clk in phase—indicating that the VCO is running relatively fast—the duration of pulse signal DN increases—thereby causing VCO 18 achieve an oscillation frequency at which signal Clk is frequency-locked and phase-locked with signal REF. Signal Clk is considered to be locked to signal REF if its frequency is within a predetermined frequency range of signal REF and the phase of signals CLK and REF are aligned. Signal Clk is considered to be out-of-lock with signal REF if its frequency is outside the predetermined frequency range of signal REF.
When the input reference clock to a PLL changes phase, the PLL must slew to the new phase. Such a condition may happen when, for example, the PLL switches from one reference clock to another clock with the same frequency but a different phase. Such a condition may also happen if the clock that the PLL switches to has a different frequency than the clock the PLL switches from. Furthermore, in some applications it is desirable to have the PLL output clock switch slowly, and not rapidly, to the new phase so as to enable other down-stream circuits to maintain proper operation.
When the input clock to a PLL misses a pulse or becomes inactive, the output of the Phase-Frequency detector 12 gets stuck in the down state until such time as the input clock becomes active again. Referring to FIGS. 1 and 2 concurrently, a clock signal, such as REFideal, applied to a PLL ideally should not have missing pulses. However, in practical applications, a clock signal such as REFactual, actually received by a PLL includes missing pulses. The phase of the feedback signal CLK generated in response to clock signal REFactual begins to vary as a result of the missing pulses. These phase shifts Δφ1 and Δφ2 are shown in FIG. 2 relative to the ideal clock signal REFideal.
When signal DN remains in a high state as a result of the missing pulses, the charge pump disposed in the PLL starts to remove charge from the loop filter. This causes signal Vcntrl generated by charge pump 14 to droop, in turn causing the VCO output phase to move away from its ideal value.
In accordance with one known technique, such as that described in U.S. Pat. No. 6,483,389, phase-frequency detector 12 is reset to prevent an extended output pulse. At best, such a technique would reset the phase-frequency detector 12 one half cycle after the missing pulse. The technique also fails to provide a compensating pulse to cancel the initial error pulse. For example, if a missing pulse on the input clock causes signal DN to be active for an extended period, no compensating UP pulse is generated to supply the charges removed in response to signal DN.
In accordance with another prior art technique, such as that described in U.S. Pat. No. 6,590,949, signal DN is pulse-width limited to limit its duration. A missing pulse detection circuit that compares the CLK input to the feedback clock, creates a compensating UP pulse to cancel out the DN pulse, as shown in FIG. 3. However, the compensating pulse takes several clock cycles to arrive, during which time the phase error continues to accumulate. Also, while the UP pulse returns the voltage input to the VCO back to normal, it does not return the phase output of the VCO back to normal, in other words, it simply stops further phase error from accumulating.